Cyclic Segmented Parallel Prefix

The cyclic segmented parallel prefix (CSPP) circuit is a varation on parallel prefix. Whereas ordinary parallel prefix computes prefix sums of a vector from the beginning, CSPP allows the starting point to move arbitrarily, with the data “wrapping around.” The wraparound is widely useful. We have used CSPP to redesign many components of a superscalar processor to run in time logarithmic in the number of inputs. Parallel-Prefix circuits and Segmented-Parallel-Prefix circuits are well understood. See for example, [1] for a discussion of log-depth Parallel-Prefix circuits. Segmented-Parallel-Prefix circuits are in an exercise of [1], and were implemented in the CM-5 supercomputer [7, 5, 4, 2]. The rest of this paper is organized as follows. Section 1 reviews the parallel-prefix problem along with the standard solutions. Section 2 reviews the standard log-depth circuits for solving parallel prefix. Section 3 reviews segmented parallel prefix. Section 4 discusses a few minor variations on parallel prefix. Section 5 describes the cyclic segmented parallel prefix problem. Section 6 discusses more minor varations. Section 7 shows some examples.